EDN - Voice of the Engineer
WEBThe Memory that Breathes. In this podcast episode, Sally talks to 4DS’ Peter Himes about the company’s ReRAM persistent memory and much more. Electronic Design News (EDN) is an electronics community for engineers, by engineers. Find the latest articles, magazines, tools, and blogs in the industry.
USB Type-C PD 3.0 Specification, Charging and Design - EDN
WEBJun 25, 2021 · The first one—Power Delivery 2.0—supports fixed output voltages including 5, 9, 12, 15, or 20V at specific operating currents, for example 3 A. The second specification—PD 3.0—includes programmable power supply (PPS), a feature that allows the USB Type-C charger’s output voltage to be adjusted in …
Eye Diagram Basics: Reading, Analyzing and Applying
WEBDec 16, 2011 · An eye diagram is a common indicator of the quality of signals in high-speed digital transmissions. An oscilloscope generates an eye diagram by overlaying sweeps of different segments of a long data stream driven by a master clock. The triggering edge may be positive or negative, but the displayed pulse that appears after a delay period may go ...
Setup and Hold Time Basics - EDN
WEBApr 19, 2012 · Hold time is defined as the minimum amount of time after the clock’s active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.
Setup and Hold Time Equations and Formulas - EDN
WEBAug 10, 2012 · Hence to fulfill the setup time requirement, the formula should be like the following. T c2q + T comb + T setup ≤ T clk + T skew (1) Let’s have a look at the timing diagram below to have a better understanding of the setup and hold time. Figure 2 Setup and hold timing diagram. Now, to avoid the hold violation at the launching flop, the data ...
16 Ways To Fix Setup and Hold Time Violations - EDN
WEBDec 8, 2021 · It will help solve any hold violations. 3. Increase the clock-q delay of launch flip-flop. Similar to the previous fix, by choosing a flop that has more clock-q delay, delay can be induced in data path logic. It will ease timing and help solve hold time violations. 4. Use a slower cell for launch flip-flop.
Equalization Techniques: CTLE, DFE, FFE, and Crosstalk - EDN
WEBOct 21, 2015 · DFE (decision feedback equalization) uses a decision circuit as part of its feedback loop. CTLE technology doesn’t change for PAM4 signaling. Tx FFE doesn’t change in principle, though with four different symbol levels, it changes in practice. But with four distinct “decisions” to feed back to the decision circuit, DFE differs for PAM4.
Audio levels, dBu, dBV, and the gang: What you need to know
WEBApr 18, 2017 · Here’s what you need to know. First off, you need to know that I expended significant effort to avoid naming this article “ dB or not dB, that is the question ”. But seriously: The vast majority of line-level analog audio interfaces fall into two categories: Advertisement. Unbalanced, using “RCA” connectors, at a so-called “-10dBV ...
Cross Sectional Area Of Wire: Formula & Calculation - EDN
WEBNov 15, 2016 · How to find the cross sectional area of a wire. First, we define that the diameter of our wire is taken in thousandths of an inch where one one-thousandth of an inch is called “one mil.”. Thus, 0.001 inch = 1 mil, 0.01 inch = 10 mils and so forth. Then we define the cross sectional area simply as the square of the wire’s diameter in mils ...
What does GT/s mean, anyway? - EDN
WEBMar 1, 2007 · When announcing version 2.0 of the PCI Express (PCIe) standard in January, the PCI Special Interest Group (PCI-SIG) said that the new version “doubles the interconnect bit rate from 2.5 GT/s to 5 GT/s.”. Most of us are used to seeing bus speeds specified in Gbps, or gigabits per second, but GT/s stands for gigatransfers per second.