EDN

Dual PLL Spread Spectrum Clock Generator

The AD9577 provides a multioutput clock generator function along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on ...
Business Wire

Codasip looks to Silicon Creations’ PLL to drive RISC-V Automotive Safety-Critical Core

ATLANTA--(BUSINESS WIRE)--Silicon Creations, a leading provider of high-performance analog and mixed-signal intellectual property (IP) today announced that its low-area integer PLL has been ...
EDN

PLL Dynamic Reconfiguration

The clock management tiles (CMT) in the Spartan-6 devices contain two DCMs and one PLL. One of the most powerful features of the PLL is its ability to dynamically reconfigure the phase, duty cycle, ...