New Electronics

Cadence Design IP portfolio in TSMC’s N5 Process gains broad adoption

Cadence Design Systems has announced that a wide range of semiconductor and system customers have now adopted Cadence Design IP in TSMC’s 5nm process technology. Designed to the latest ...
Nasdaq

Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

DSP-based, flex-rate multi-rate SerDes IP is optimized for PPA for next-generation compute, switching, storage, AI/ML and 5G SoCs New architecture offers 25% power improvement, 40% area reduction and ...
Nasdaq

Cadence Announces New Low-Power IP for PCI Express 5.0 Specification on TSMC N5 Process

Long-reach, high-performance PCIe 5.0 IP with ultra-low power consumption targets hyperscale computing, networking and storage applications SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, ...
Design-Reuse

Cadence Introduces Industry's Leading-Performance, Silicon-Proven 22Gbps GDDR6 IP at TSMC N5

SAN JOSE, Calif.— November 16, 2022-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Cadence ® IP for GDDR6 is silicon proven on TSMC’s N5 process technology, exceeding Cadence’s ...
Design-Reuse

Synopsys DesignWare IP Achieves Broad Industry Adoption with Multiple First-Pass Customer Silicon Successes on TSMC's N5 Process

High-Quality Interface and Foundation IP Adopted by More Than 20 Leading Semiconductor Companies, Across Range of Automotive, Mobile and High-Performance Computing Markets MOUNTAIN VIEW, Calif., June ...
Business Wire

Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, ...