EDN

Xilinx uses Unitive’s eutectic wafer-bumping process to lower FPGA costs

RESEARCH TRIANGLE PARK, N.C. — Flip-chip technology supplier Unitive Inc. here today announced qualification of its eutectic wafer-bumping process for volume production of high-density ...
AZOM

Optimizing the Manufacturing Process of Semiconductors Using Pressure Sensors

This higher density of circuitry on a wafer requires greater accuracy and a highly fragile and advanced fabrication process. Several newer and highly complex ICs today are made of a dozen or more ...
Aviation Week

WAFER BUMPING

Interconnect, a wafer bumping service company, announced qualification of its Ni/Au pad resurfacing process for high-temperature wire bond applications, producing bonds that are stable at high ...
Semiconductor Engineering

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during ...