Once TestBencher generates VHDL and Verilog test benches, they can be optionally linked to C++ code via the TestBuilder C++ library.

The use of FPGAs for complex processing can create an overall design that may combine C, VHDL and Verilog. This creates a challenge when it comes to verification, and a particular challenge to the new ...

It produces target-independent Verilog and VHDL code and test benches for implementing and verifying ASICs and FPGAs.